A cache memory device that includes a main memory and a cache memory and pre-reads data at a look-ahead address from the main memory into the cache memory has been known. Determining, for example, a look-ahead address by an address calculation circuit based on cache control information accompanying data in such a device is currently being discussed (see, for example, Japanese Laid-open Patent Publication No. 9-259040).
According to conventional technology, it is necessary to add cache control information to data as a means to improve the hit ratio of cache and thus, more memory is needed for the added information and access efficiency to the memory falls. Thus, data processing is delayed. When it is assumed that a processor accesses data, data including cache control information has no general versatility.